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cy23fs08 failsafe? 2.5 v/3.3 v zero delay buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07518 rev. *f revised january 7, 2011 features internal dcxo for continuous glitch-free operation zero input-output propagation delay 100 ps typical output cycle-to-cycle jitter 110 ps typical output-output skew 1 mhz to 200 mhz reference input supports industry standard input crystals 200 mhz (commercial), 166 mhz (industrial) outputs 5 v-tolerant inputs phase-locked loop (pll) bypass mode dual reference inputs 28-pin ssop split 2.5 v or 3.3 v output power supplies 3.3 v core power supply industrial temperature available functional description the cy23fs08 is a failsafe? zero delay buffer with two reference clock inputs and eight phase-aligned outputs. the device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. continuous, glitch-free operation is achieved by using a dcxo, which serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock. the unique feature of the cy23fs 08 is that the dcxo is in fact the primary clocking source , which is synchronized (phase-aligned) to the external reference clock. when this external clock is restored , the dcxo automatically resynchronizes to the external clock. the frequency of the crystal connected to the dcxo, must be chosen to be an integer factor of the frequency of the reference clock. this factor is set by four select lines: s[4:1]. see table 2 . the cy23fs08 has three split power supplies; one for core, another for bank a outputs, and the third for bank b outputs. each output power supply, except vddc can be connected to either 2.5 v or 3.3 v. vddc is the power supply pin for internal circuits and must be connected to 3.3 v. clka[1:4] clkb[1:4] dcxo decoder 4 failsafe tm block pll xin xout 4 4 ref2 fbk s[4:1] fail# /safe ref1 refsel logic block diagram [+] feedback
cy23fs08 document number: 38-07518 rev. *f page 2 of 15 contents features............................................................................. 1 functional description..................................................... 1 logic block diagram........................................................ 1 contents ............................................................................ 2 pinouts .............................................................................. 3 failsafe function.............................................................. 4 xtal selection criteria and application example ...... 8 absolute maximum conditions..................................... 10 recommended pullable crystal specifications ........... 10 operating conditions..................................................... 10 dc electrical characteristics ........................................ 11 switching characteristics.............................................. 11 ordering information....................................................... 11 package diagram............................................................ 12 document history page ................................................. 13 sales, solutions, and legal information ...................... 14 worldwide sales and design supp ort............. .......... 14 products .................................................................... 14 psoc solutions ......................................................... 14 [+] feedback
cy23fs08 document number: 38-07518 rev. *f page 3 of 15 pinouts figure 1. pin configuration clkb1 s2 s3 vddb clkb2 s4 vddb xin vddc fail#/safe 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 cy23fs08 28-pin ssop ref1 ref2 vssb refsel fbk vssa clka1 clka2 s1 vdda 9 10 11 12 13 14 vssb clkb3 clkb4 20 19 18 17 16 15 vssa clka3 clka4 vdda xout notes 1. for normal operation, connect either one of the eight clock outputs to the fbk input. 2. weak pull downs on all clk outputs. 3. weak pull ups on these inputs. 4. weak pull downs on these inputs. table 1. pin definitions pin number pin name description 1,2 ref1,ref2 reference clock inputs. [4] 5 v tolerant. 4,5,10,11 clkb[1:4] bank b clock outputs . [1, 2] 25,24,19,18 clka[1:4] bank a clock outputs. [1, 2] 27 fbk feedback input to the pll . [1] 23,6,7,22 s[1:4] frequency select pins/pll and dcxo bypass . [3] 14 xin reference crystal input . 15 xout reference crystal output . 16 fail#/safe valid reference indicator . a high level indicates a valid reference input. 13 vddc 3.3 v power supply for the internal circuitry . 8,12 vddb 2.5 v or 3.3 v power supply for bank b outputs . 3,9 vssb ground . 17,21 vdda 2.5 v or 3.3 v power supply for bank a outputs . 20,26 vssa ground . 28 refsel reference select . selects the active reference cl ock from either ref1 or ref2. when refsel = 1, ref1 is selected. when refsel = 0, ref2 is selected. table 2. configuration table s[4:1] xtal (mhz) ref(mhz) out(mhz) ref:out ratio ref:xtal ratio out:xtal ratio min max min max min max 0000 pll and dcxo bypass mode 1000 8.33 30 16.67 60.00 8.33 30.00 ? 22 1 1110 9.50 30 57.00 180.00 28.50 90.00 ? 26 3 [+] feedback
cy23fs08 document number: 38-07518 rev. *f page 4 of 15 failsafe function the cy23fs08 is targeted at cloc k distribution applications that requires or may require continued operation if the main reference clock fails. existing approaches to this requirement have used multiple reference clo cks with either internal or external methods to switch between references. the problem with this technique is that it leads to interruptions (or glitches) when transitioning from one reference to another, often requiring complex external circuitry or software to mainta in system stability. the technique implemented in this design comple tely eliminates any switching of references to the pll, gr eatly simplifying system design. the cy23fs08 pll is driven by the crystal oscillator, which is phase-aligned to an external re ference clock so that the output of the device is effectively phas e-aligned to reference via the external feedback loop. this is accomplished by using a digitally controlled capacitor array to pull the crystal frequency over an approximate range of 300 ppm from its nominal frequency. in this mode, if the reference frequency fails (that is, stops or disappears), the dcxo maintains its last setting and a flag signal (fail#/safe) is set to indicate failure of the reference clock. the cy23fs08 provides four se lect bits, s1 through s4 to control the reference to crystal frequency ratio. the dcxo is internally tuned to the phase and frequency of the external reference only when the reference frequency divided by this ratio is within the dcxo capture range. if the frequency is out of range, a flag is set on the fa il#/safe pin not ifying the system that the selected reference is not valid. if the reference moves in range, then the flag is cleared, indicating to the system that the selected reference is valid. figure 2. fail#/safe timing for input reference failing catastrophically 0101 8.50 30 6.80 24.00 1.70 6.00 ? 44/5 1/5 1011 8.33 30 25.00 90.00 6.25 22.50 ? 43 3/4 0011 8.33 30 2.78 10.00 2.78 10.00 1 1/3 1/3 1001 8.33 30 8.33 30.00 8.33 30.00 1 1 1 1111 8.00 25 32.00 100.00 32.00 100.00 1 4 4 1100 8.00 25 64.00 200.00 64.00 200.00 1 8 8 0001 8.33 30 1.04 3.75 2.08 7.50 2 1/8 1/4 0110 8.33 30 4.17 15.00 8.33 30.00 2 1/2 1 1101 8.33 30 16.67 60.00 33.33 120.00 2 2 4 0100 8.33 30 4.17 15.00 16.67 60.00 4 1/2 2 1010 8.33 30 12.50 45.00 50.00 180.00 4 3/2 6 0010 8.33 30 1.39 5.00 11.11 40.00 8 1/6 4/3 0111 8.33 30 6.25 22.50 50.00 180.00 8 3/4 6 table 2. configuration table (continued) s[4:1] xtal (mhz) ref(mhz) out(mhz) ref:out ratio ref:xtal ratio out:xtal ratio min max min max min max ref out fail#/safe t fsl t fsh [+] feedback
cy23fs08 document number: 38-07518 rev. *f page 5 of 15 figure 3. fail#/saf e timing formula figure 4. failsafe timing diagram: input reference slowly drifting out of failsafe capture range table 3. failsafe timing table parameter description conditions min max unit t fsl fail#/safe assert delay measured at 80% to 20%, load = 15 pf see figure 3 ns t fsh fail#/safe deassert delay measured at 80% to 20%, load = 15 pf see figure 3 ns reference + 300 ppm reference - 300 ppm reference output + 300 ppm output - 300 ppm output fail#/safe t fsh reference off t fsl time frequency volt [+] feedback
cy23fs08 document number: 38-07518 rev. *f page 6 of 15 figure 5. failsafe refe rence switching behavior because of the dcxo architecture, the cy23 fs08 has a much lower bandwidth than a typical pll-based clock generator. this is shown in figure 6 . this low bandwidth makes the cy23fs08 also useful as a jitter attenuator. the loop bandwidth curve is also known as the jitter transfer curve. figure 6. failsafe effective loop bandwidth (min) [+] feedback
cy23fs08 document number: 38-07518 rev. *f page 7 of 15 figure 7. duty cycle figure 8. input slew rate figure 9. output slew rate figure 10. output to output skew and intrabank skew figure 11. part to part skew t 1 t 2 duty cycle - t dc v dd /2 v dd /2 v dd /2 v dd 0v = t 1 / t 2 t sr(i) v dd 0v 30% 70% 70% 30% t sr(i) t sr(o) v dd 0v 20% 80% 80% 20% t sr(o) v dd /2 v dd /2 t sk fbk, part 1 v dd /2 t sk(pp) v dd /2 fbk, part 2 [+] feedback
cy23fs08 document number: 38-07518 rev. *f page 8 of 15 figure 12. phase offset xtal selection criteria and application example selecting the appropriate xtal ensures the failsafe device is able to span an appropriate frequency of operation. also, the xtal parameters determine the holdover frequency stability. critical parameters are given here. cypress recommends that you choose: low c0/c1 ratio (240 or less) so that the xtal has enough range of pullability. low temperature frequency variation low manufacturing frequency tolerance low aging c0 is the xtal shunt capacitance (3 pf to 7 pf typ). c1 is the xtal motional capacitance (10 ff to 30 ff typ). the capacitive load as ?seen? by the xtal is across its terminals. it is named c loadmin (for minimum value), and c loadmax (for maximum value).these are used for calculating the pull range. note that the c load range ?center? is approximately 20 pf, but we may not want a xtal calibrated to that load. this is because the pullability is not linear, as represented in the equation below. plotting the pullability of the xt al shows this expected behavior as shown in figure 13 . in this example, specifying a xtal calibrated to 14 pf load provides a balanced ppm pullability range around the nominal frequency. example: c loadmin = (12 pf ic input cap + 0 pf pulling ca p + 6 pf trace cap on board) / 2 = 9 pf c loadmax = (12 pf ic input cap + 48 pf pulling cap + 6 pf trace cap on board) / 2 = 33 pf pull range = (fc loadmin ? fc loadmax ) / fc loadmin = (c1 / 2) * [(1 / (c0 + c loadmin )) ? (1 / (c0 + c loadmax ))] pull range in ppm = (c1 / 2) * [(1 / (c0 + c loadmin )) ? (1 / (c0 + c loadmax ))] * 10 6 ref v dd /2 t ( ? ) v dd /2 fbk [+] feedback
cy23fs08 document number: 38-07518 rev. *f page 9 of 15 figure 13. frequency vs. c load behavior for example xtal calculated value of the pullability range for the xtal with c0/c1 ratio of 200, 300, and 400 are shown in table 4 . for this calculation c loadmin = 8 pf and c loadmax = 32 pf is used. using a xtal that has a nominal frequency specified at load capacitance of 14 pf, almost symmetrical pullability range is obtained. next, it is important to calculate the pullability range including error tolerances. this is the capture range of the input reference frequency that the failsafe device and xtal combination can reliably span. calculating the capture range involves subtracting error tolerances as follows: parameter ........................................................ f error (ppm) manufacturing frequency toleranc e ...................................15 temperature stability ..........................................................30 aging ................................................................................... 3 board/trace variation ........................................................... 5 total ...................................................................................53 example: capture range for xtal with c0/c1 ratio of 200 negative capture range = ?385 ppm + 53 ppm = ?332 ppm positive capture range = 333 ppm ? 53 ppm = +280 ppm it is important to note that the xtal with lower c0/c1 ratio has wider pullability/capture range as compared to the higher c0/c1 ratio. this helps to select the appropriate xtal for use in the failsafe application. pullability range vs. c load (normalized to 14pf c load ) -400 -300 -200 -100 0 100 200 300 400 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 c load (pf) delta freq. from nominal (ppm) c0/c1 = 200 c0/c1 = 300 c0/c1 = 400 table 4. pullability range from xtal with different c0/c1 ratio c0/c1 ratio c loadmin c loadmax pullability range 200 8 32 ?385 333 300 8 32 ?256 222 400 8 32 ?192 166 [+] feedback
cy23fs08 document number: 38-07518 rev. *f page 10 of 15 absolute maximum conditions exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. parameter description condition min max unit v dd supply voltage ?0.5 4.6 v v in input voltage relative to v ss ?0.5 v dd + 0.5 vdc t s temperature, storage non functional ?65 150 c t j temperature, junction functional ? 125 c esd hbm esd protection (human body model ) mil-std-883, method 3015 2000 ? v ? jc dissipation, junction to case mil-spec 883e method 1012.1 36.17 c/w ? ja dissipation, junction to ambient jedec (jesd 51) 100.6 c/w ul?94 flammability rating at 1/8 in. v?0 msl moisture sensitivity level 1 multiple supplies : the voltage on any input or i/o pin cannot exceed the power pi n during power-up. power supply sequencing is not required. recommended pullable crystal specifications [5] parameter name comments min typ max unit f nom nominal crystal frequency parallel resonance, fundamental mode, at cut 8.00 ? 30.00 mhz c lnom nominal load capacitance ? 14 ? pf r 1 equivalent series resistance (esr) fundamental mode ? ? 25 ? r 3 /r 1 ratio of third overtone mode esr to fundamental mode esr ratio used because typical r 1 values are much less than the maximum spec 3? ? dl crystal drive level no external series resistor assumed ? 0.5 2 mw f 3sepli third overtone separation from 3*f nom high side 300 ? ? ppm f 3seplo third overtone separation from 3*f nom low side ? ? ?150 ppm c0 crystal shunt capacitance ? ? 7 pf c0/c1 ratio of shunt to motional capacitance 180 ? 250 c1 crystal motional capacitance 14.4 18 21.6 ff operating conditions parameter description min max unit v ddc 3.3 v supply voltage 3.135 3.465 v v dda, v ddb 2.5 v supply voltage range 2.375 2.625 v 3.3 v supply voltage range 3.135 3.465 v t a ambient operating temperature, commercial 0 70 c ambient operating temperature, industrial ?40 85 c c l output load capacitance (fout < 100 mhz) ? 30 pf output load capacitance (fout > 100 mhz) ? 15 pf c in input capacitance (except xin) ? 7 pf c xin crystal input capacitance (all internal caps off) 10 13 pf t pu power up time for all vdds to reach minimum specified voltage (power ramps must be monotonic) 0.05 500 ms note 5. ecliptek crystals ecx-5788-13.500m, ecx-5807-19.440m, ecx-587 2-19.53125m, ecx-6362-18.432m, ecx-5808-27.000m, ecx-5884-17.664 m, ecx-5883-16.384m, ecx-5882-19.200m, ecx-5880 -24.576m meet these specifications. [+] feedback
cy23fs08 document number: 38-07518 rev. *f page 11 of 15 dc electrical characteristics parameter description test conditions min typ max unit v il input low voltage cmos levels, 30% of v dd ? ? 0.3v dd v v ih input high voltage cmos levels, 70% of v dd 0.7v dd ??v i il input low current v in = v ss (100k pull up only) ? ? 50 a i ih input high current v in = v dd (100k pull down only) ? ? 50 a i ol output low current v ol = 0.5 v, v dd = 2.5 v ? 18 ? ma v ol = 0.5 v, v dd = 3.3 v ? 20 ? ma i oh output high current v oh = v dd ? 0.5 v, v dd = 2.5 v ? 18 ? ma v oh = v dd ? 0.5 v, v dd = 3.3 v ? 20 ? ma i ddq quiescent current all inputs grounded, pll and dcxo in bypass mode, reference input = 0 ??250a switching characteristics parameter [7] description test conditions min typ max unit f ref reference frequency commercial grade 1.04 ? 200 mhz industrial grade 1.04 ? 166.7 mhz f out output frequency 15 pf load, commercial grade 1.70 ? 200 mhz 15 pf load, industrial grade 1.70 ? 166.7 mhz f xin dcxo frequency 8.0 ? 30 mhz t dc duty cycle measured at v dd /2 47 ? 53 % t sr(i) input slew rate measured on re f1 input, 30% to 70% of v dd 0.5 ? 4.0 v/ns t sr(o) output slew rate measured from 20% to 80% of v dd = 3.3v, 15 pf load 0.8 ? 4.0 v/ns measured from 20% to 80% of v dd =2.5v, 15 pf load 0.4 ? 3.0 v/ns t sk(o) output to output skew all output s equally loaded, measured at v dd /2 ? 110 200 ps t sk(ib) intrabank skew all outputs equally loaded, measured at v dd /2 ? ? 75 ps t sk(pp) part to part skew measured at v dd /2 ? ? 500 ps t ( ? ) [6] static phase offset measured at v dd /2 ? ? 250 ps t d( ? ) [6] dynamic phase offset measured at v dd /2 ? ? 500 ps t j(cc) cycle-to-cycle jitter load = 15 pf, f out ?? 6.25 mhz ? 100 200 ps ?1835ps rms t lock lock time at room temperature with 18.432 mhz crystal ? 70 ? ms ordering information part number package type product flow pb-free cy23fs08oxi 28-pin ssop industrial, ?40 c to 85 c cy23fs08oxit 28-pin ssop ? tape and reel industrial, ?40 c to 85 c CY23FS08OXC 28-pin ssop commercial, 0 c to 70 c CY23FS08OXCt 28-pin ssop ? tape and reel commercial, 0 c to 70 c notes 6. the t ( ? ) reference feedback input delay is guaranteed for a maximum 4:1 input edge ratio between the two signals as long as t sr(i) is maintained. 7. parameters guaranteed by design and characterization, not 100% tested in production. [+] feedback
cy23fs08 document number: 38-07518 rev. *f page 12 of 15 ordering code definition package diagram figure 14. 28-pin (5.3 mm) shrunk small outline package sp28 package type: t = tape and reel, blank = tube temperature code: c = commercial, i = industrial package: 28-pin ssop, pb-free device number cy23fs08 ox x (t) 51-85079 *d [+] feedback
cy23fs08 document number: 38-07518 rev. *f page 13 of 15 acronyms document conventions units of measure acronym description dcxo digitally controlled crystal oscillator esd electrostatic discharge pll phase locked loop rms root mean square ssop shrunk small outline package xtal crystal symbol unit of measure ? c degree celsius a micro amperes ma milli amperes ms milli seconds mhz mega hertz ns nano seconds pf pico farad ps pico seconds ppm parts per million wwatts ? ohms vvolts [+] feedback
cy23fs08 document number: 38-07518 rev. *f page 14 of 15 document history page document title: cy23fs08 failsafe? 2.5 v/3.3 v zero delay buffer document number: 38-07518 rev. ecn no. submission date orig. of change description of change ** 123699 04/23/03 rgl new data sheet *a 224067 see ecn rgl/zjx changed the xtal specifications table. *b 276749 see ecn rgl removed (t lock ) lock time specification. *c 417645 see ecn rgl added lead-free devices added typical nos. on jitters *d 2865396 01/25/2010 kvm remove figures showing dy namic response to 180 phase change to ref add waveforms for input slew rate and intrabank skew change ?cl? to ?c load ? absolute maximum conditions table: remove duplicate t a parameter replace crystal ecx?5806?18.432m with ecx?6362?18.432m remove obsolete part numbers cy 23fs08oi, cy23fs08oit, cy23fs08oc and cy23fs08oct replace ?lead-free? with ?pb-free? remove unreferenced footnote 9 change package drawing title from ?o28? to ?sp28?, updated package diagram added table of contents *e 2925613 04/30/10 kvm posting to external web. *f 3130032 01/06/2011 bash changed t d( ? ) max value from 200 to 500 and removed t d( ? ) typical value in switching characteristics on page 11. added ordering code definition . added acronyms and units of measure on page 13. [+] feedback
document number: 38-07518 rev. *f revised january 7, 2011 page 15 of 15 failsafe is a trademark of cypress semiconductor. all product and company names mentioned in this document are the trademarks o f their respective holders. cy23fs08 ? cypress semiconductor corporation, 2003-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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